The invention relates to latch circuits, and more particularly to a method of testing connectivity using latch signals which are transmitted as differential pairs of signals.
Latches take a variety of forms and are used in a variety of applications. Latches are basic building blocks of many types of sequential digital circuits including flip-flops, registers, adders, multipliers, etc., and are used at interfaces between digital circuits and analog circuits. In its simplest form, a binary digital latch is implemented by a circuit which generates an output signal having one of two binary states determined in accordance with a state of at least one input signal. A clock signal times the operation of the binary latch such that the output signal transitions between states at times determined in accordance with the clock signal.
A current mode logic (“CML”) latch is a particular type of latch which is usable when signals are transmitted as differential pairs of signals. Signals transmitted at relatively high frequencies require noise rejection to a greater degree than signals transmitted at lower frequencies. One way to achieve greater noise rejection is to transmit one signal differentially as a pair of signals which have opposite states. In each such pair, the differential signals either remain together at their respective opposite states or swing between the opposite states simultaneously. Data-carrying signals are input to a CML latch as a pair of differential data signals. Clock signals are input to the CML latch as a pair of differential clock signals. A CML latch rejects noise that affects (e.g., slows, advances, raises or lowers) both of the differential signals in the same way so as to latch the output signal reliably at a correct state despite noise affecting the differentially transmitted pair of signals. With differential signal transmission, even in the presence of noise, the differential clock signals accurately time the operation of the CML latch and the CML correctly latches the states of the differential data signals.
FIG. 1 is a schematic diagram illustrating a CML latch 100 in accordance with the prior art. As illustrated in FIG. 1, the CML latch 100 includes a first input device 102 and a second input device 104, the first and second input devices being operable to receive first and second differentially transmitted input signals AP and AN, respectively. A first tail device 110 controls the flow of current between the first and second input devices and a current source 114 which is connected to ground. The first and second input devices 102, 104 become active when one clock signal CP input to the first tail device 110 is active. Such clock signal CP is one of a pair of differential clock signals CP and CN having phases 180 degrees apart, the clock signals swinging simultaneously between opposite levels. The differential clock signals operate at a relatively high frequency, such as a frequency of a few hundred megahertz (MHz) to several gigahertz (GHz) or tens of gigahertz.
When clock signal CP is active, one of the first and second input devices conducts a current I1 or I2, respectively, in accordance with the states of the first and second input signals AP and AN, respectively. The states of output signals ZP and ZN change according to the currents I1 and I2 across loads L1 and L2, respectively. In such way, when input signal AP is active, current I1 across load L1 pulls down the voltage at node ZN such that the output signal ZN becomes low. The input signal AN at such time is inactive, causing input device 104 to be turned off. In that case, current I2 does not flow and the output signal at node ZP remains high. On the other hand, when input signal AN is active, current I2 across load L2 pulls down the voltage at node ZP such that the output signal ZP becomes low. At such time, the input signal AP is inactive, causing input device 102 to be turned off such that current I1 does not flow and the output signal at node ZN remains high.
A pair of cross-coupled devices 106 and 108 are operable to latch the output signals ZP and ZN when the differential clock signal CN is active. When clock signal CP is active, the clock signal CN is inactive, such that output signals ZP and ZN change when the input signals AN and AP change. On the other hand, when clock signal CP is inactive and the clock signal CN is active, the cross-coupled devices 106, 108 latch the current states of the output signals ZP and ZN and hold them until clock signal CP becomes active again.
One problem of the CML latch 100 is that it is only usable when the differential clock signals CP and CN are active. The high switching frequency of these clock signals precludes them from being supplied to the CML latch by any means other than internal generation on an integrated circuit (“IC”) or chip which incorporates the CML latch or on a card to which the chip is mounted. Signals cannot be propagated through the CML latch unless the differential clock signals are present.
However, it is desirable to test chips which include CML latches at times when it is not possible to supply the differential clock signals CP and CN to the latches.